1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit devices, and more specifically to dual port memory devices.
2. Description of the Prior Art
Computer systems utilize cache memories to enhance system performance. A data cache contains the cached data, and a cache tag memory contains the addresses of data stored in the cache. A processor, when making a memory access, accesses the desired memory location through the cache. If the desired location is already in the cache, access is complete. If it is not, the memory location is fetched from main system memory and loaded into the cache.
The speed of the integrated circuit devices used in the cache are important. The cache tag memory must provide a hit or a miss signal for every memory access by the processor. If the cache tag memory is slightly slow, the performance of the entire system suffers.
As is known in the art, one technique to improve the operating speed of integrated circuit devices is to reduce or balance stray capacitances. Memories have relatively long bit lines which contribute significantly to such capacitances. Good device design can help minimize such capacitances, but the nature of a memory device causes inevitable problems. Therefore, balancing of bit lines in a memory device layout is important.
No successful design has previously been done for a dual port cache tag memory device. In such a device, the capacitances for two sets of bit lines must be considered. In addition to stray capacitances, coupling capacitances between bit lines for the two ports can adversely impact device performance. In a dual port cache tag memory, in which speed is important, the extra problems caused by the extra bit lines can be significant.
Any device used in specialty designs such as cache tag memories must take special device functions into consideration. For example, cache tag memories must occasionally be cleared. One technique for clearing cache memories utilizes a flash clear, which clears only a single bit position within the memory. The cleared bit position is reset for all entries in the memory simultaneously. This allows the entire memory to be reset in a single step.
Special functions such as flash clear must be properly handled by any device design. Designs which improve device speed often do so at the expense of being able to handle more complex functions. Devices which can perform more complex functions such as flash clear often must sacrifice speed in order to do so.
It would be desirable to provide a dual port cache tag memory device which minimizes stray and cross coupling capacitances to obtain increased speed while retaining the ability to perform functions such as flash clear. Such a device preferably does so without greatly increased design complexity.